A Flexible Message Passing Mechanism for Objective VHDL

When defining an object-oriented extension to VHDL, the necessary message passing is one of the most complex issues and has a large impact on the whole language. This paper identifies the requirements for message passing suited to model hardware and classifies different approaches. To allow abstract communication and reuse of protocols on system level, a new, flexible message passing mechanism proposed for Objective VHDL1 will be introduced. 1 Structure of the paper The introduction explains the general purpose and issues of message passing. Additionally, some basic terms are introduced. The third chapter illuminates different aspects of message passing to identify the related requirements—especially for hardware design—and shows the implications to the whole language. To allow an estimation of message passing mechanisms, a classification scheme is proposed in Chapter 4. Chapter 5 describes and classifies two message passing mechanisms of currently most discussed approaches for object-oriented extensions to VHDL. Finally, a very flexible message passing mechanism for a new object-oriented extension of VHDL—Objective VHDL—is proposed and classified.